1. Technical Field
The present invention relates to a termination of a semiconductor memory device. More particularly, the present invention relates to a synchronous semiconductor memory device having an on-die termination circuit, and an on-die termination method for a synchronous semiconductor memory device.
2. Description
Various kinds of semiconductor devices realized through an integrated circuit chip, such as CPUs, memories and gate arrays etc., are incorporated with one another in various electronic products such as personal computers, servers or workstations. A tendency toward a high-speed operation of such electronic products brings about a small swing width of an interface signal between the semiconductor devices, in order to reduce a delay time taken in a signal transfer. However, such a trend that the swing width of the signal gradually becomes small, has influence upon external noise, and further, a back-echo caused by an impedance mismatch in an interface terminal becomes critical. The impedance mismatch is generated by external noise or a variation of a power voltage, a change of an operating temperature, a change of a manufacturing process, etc. The impedance mismatch can cause a difficulty in a high-speed transmission of data and a distortion in output data. If a distorted output signal is transmitted, a set-up/hold time failure or an error in a decision of an input level, etc., may be often caused at a receiving side.
In particular, the frequency of a signal bus in electronic products employing a dynamic random access memory (DRAM) is being strikingly increased to realize a high-speed operation, and bus termination techniques are being variously researched to reduce a distortion phenomenon against a signal integrity by solving the impedance mismatching problem. As a result of this research, it is known that a system using on-die termination (ODT) is more advantageous from a viewpoint of the signal integrity than a system using a mother board termination (MBT), particularly in an electronic system having a stub bus structure.
One prior art MBT technique is disclosed in U.S. Pat. No. 5,945,886 issued on Aug. 31, 1999 to Millar. One prior art ODT technique is disclosed in U.S. Pat. No. 6,157,206 issued on Dec. 5, 2000 to Taylor et al.
The ODT has such a termination structure that a bus termination is performed at an input/output (I/O) port of a memory equipped with a memory module. That is, the ODT called an on-chip termination is realized by an impedance matching circuit that is employed at a position neighboring to a pad within an integrated circuit chip.
In a semiconductor memory device such as a synchronous DRAM (SDRAM) of a double data rate (DDR) type, etc., a typical ODT for performing an impedance matching is realized by connecting a resistance element having a fixed resistance value to the pad. For instance, if an optional termination circuit is designed to perform a termination operation of 60 ohms, resistance values of resistance elements (Rup,Rdn) constituting the termination circuit are each provided as 120 ohms as shown in FIG. 2.
Such an ODT circuit has only a fixed resistance value, thus has a difficulty to perform various termination operations in conformity to a change of a receiving environment. In other words, when the termination is pre-determined with a default value, an adaptive termination operation is impossible. Further, even though a self-termination circuit for controlling the ODT by itself is equipped internally, it is unnecessary for a semiconductor memory device in which the self-termination circuit is not required, and moreover it is not easy to control a termination resistance by using variable values of various modes through a signal applied from the outside. Furthermore, separate Direct Current (DC) on-die termination parameter and Alternating Current (AC) on-die termination parameter specifications are being recommended in high-speed semiconductor memory devices, thus an ODT countermeasure capable of satisfying such a recommended specification is needed.
Therefore, a high-speed semiconductor memory device requires an adaptive ODT technique capable of definitely satisfying the recommended ODT DC and AC parameter specifications and to perform a termination operation matched to a transmission/reception environment through an external or internal control, by realizing an ODT operation synchronized to an external clock.
Accordingly, it would be desirable to provide an On-die Termination (ODT) operation synchronized to an external clock in a synchronous semiconductor memory device having an ODT circuit, satisfying ODT DC and AC parameter specifications, and performing an adaptive impedance matching through an external or internal control.
It would also be desirable to provide an ODT circuit capable of reducing its occupation area and a power consumption. Still further, it would be desirable to provide a double data rate (DDR) type synchronous semiconductor memory device capable of performing an ODT turn-on and turn-off operation in conformity with an output of data. Accordingly, the present invention is directed to a synchronous semiconductor memory device having an ODT circuit, and an ODT method for a synchronous semiconductor device.
According to one aspect of the present invention, a synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to an external clock, includes an ODT circuit for generating ODT up and down signals with the same timing as a generation of data output up and down signals for the data output operation, to thus perform an ODT operation.
The ODT circuit includes an ODT synchronous buffer, an ODT gate and an ODT driver.
The ODT synchronous buffer receives an ODT command applied in response to a buffered clock signal that is generated by buffering an external clock, and then outputs the ODT command in response to a first clock signal delay-locked to the external clock, to thus generate a synchronous ODT command.
The ODT gate passes through and latches the synchronous ODT command in response to the first clock signal and a second clock signal that has a phase difference of a determined level from the first clock signal, to thus generate ODT up and down signals.
The ODT driver performs an ODT driving operation synchronized to the external clock, by controlling on or off operations of a pull-up resistance and a pull-down resistance in response to a state of the ODT up and down signals.
According to another aspect of the present invention, an ODT method in a synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to an external clock, includes generating ODT up and down signals at the same timing as a generation of data output up and down signals for the data output operation; and performing an ODT operation corresponding to a state of the ODT up and down signals when an ODT command is applied, to thus control a pull-up and pull-down resistance within drivers for an ODT.
The systematic and methodic configurations of the present invention realize an ODT operation synchronized to an external clock, to satisfy an on-die termination DC and AC parameter specification and perform an adaptive impedance matching through an external or internal control.